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Johnstech Technical Library

Explore Johnstech’s technical library on semiconductor testing, device contactors, RF performance, and more. Here you can access resources on optimizing test efficiency, understanding contactor specs, and addressing challenges in high-frequency testing. You can also learn about thermal modeling, pulse parameter selection, and review archived papers on socket performance and lead-free device testing. This page is updated frequently, so check back for more great presentations and technical papers.

Featured Content

  • Methods for Characterization of Large Socket Housing Deflection

    Presented in Binan, Philippines, February 2025
    by: Brian Sheposh, Director of Engineering & Valts Treibergs, Principal Custom Products Engineer

    Download Document

  • Optimal Spring Probe Solutions for Every Application

    Presented at TestConX, March 2024
    by: Valts Treibergs, Principal Custom Products Engineer

    Download Document

  • Improved Test Performance for Amplifiers

    by: Jeff Sherry, PE, MSEE, Senior RF Engineer

    Download Document

Symposia

  • The Impact of Grounding on RF Performance

  • Johnstech Seminar Series, October 2024
    Voted Most Educational Presentation, TestConX 2025
    by: Brian Sheposh, Director of Engineering, Jeff Sherry, Principal Engineer contributing

  • Addressing Test Challenges with Solid Contact Technology

  • Presented at the TestConX Workshop, March 2024
    by: Brian Sheposh, Sr. Product Engineer

  • Pulsed Current-Carrying Capacity of Small Metallic Conductors as applied to Device Test

  • Presented at the BiTS Workshop, March 2009
    Attendee Choice Award Winner

  • Understanding Specs to Better Simulate Solder-to-Board Performance

  • Presented at the BiTS Workshop, March 2012
    by: Jeff Sherry, PE, MSEE, Senior RF Engineer

Technical Papers

  • Enhancing Semiconductor Test Efficiency: The Johnstech J-Tuning Process

  • by: Johnstech Engineering Staff

  • Enhancing Semiconductor Testing: Understanding the Importance of Test Contactor Specifications

  • by: Johnstech Engineering Staff

  • Monte Carlo Simulation and Design of Experiments for Improved Pin-Pad Alignment

  • Presented at the BiTS Workshop, March 2011
    by: John DeBauche, Engineer Manager

  • Can Your Socket Handle the Heat?

  • Published in Chip Scale Review, March 2011
    by: Jeff Sherry, PE, MSEE, Senior RF Engineer

  • Thermal Modeling and Analysis of Device-Contactor-Load Board System

  • by Harlan Faller, PE, Advanced Senior Technologist

  • Choosing Pulse Parameters for High Current Testing

  • by Harlan L. Faller, PE, Lead

  • Designing the Optimal Board for IC Testing

  • Published in EE-Evaluation Engineering, September 2010
    By Jeff Sherry, PE, MSEE, Senior RF Engineer

  • CCC: What is it and Why is it Important to Your Test Outcomes?

  • by Harlan L. Faller, PE, MSEE and Jeff Sherry, PE, MSEE

Archive

Socket Performance Over Time & Insertion Count with Pb-Free Applications Download Document Presented at the BiTS Workshop, March 2006
Award Winning Paper: Best Data Presented
Challenges of Contacting Lead-Free Devices Download Document  
Optimizing the Whole Test System to Achieve Optimal Yields and Lowest Test Costs  Download Document * This paper is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the products or services of Johnstech International Corporation. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.